In a CC-NUMA system built by high performance processors, due to a limited extension capability of the processors themselves, the processors need to be grouped into multiple nodes, and multiprocessor extension is performed by using a node controller (NC), so as to increase a quantity of parallel processing processors, thereby improving performance of the CC-NUMA system.
At present, a high performance processor used in a CC-NUMA system usually has a large-capacity memory extension capability and a relatively large-capacity cache, and can perform memory extension. All processors on each node can perform coherent access to memory of other processors in the CC-NUMA system, so that a directory is designed on each code to record a situation in which data in the node is cached by a processor in another node in the CC-NUMA system except the node, where the situation includes a state of the data and a position of the processor that accesses the data, where the state of the data includes shared or exclusive.
Generally, in NC design, a directory is implemented by using a relatively large-capacity memory. However, a random error, including a read error or write error, which is caused due to an interference factor, exists in the memory. Therefore, error check needs to be performed on a directory memory. An error correction code (ECC) for single error correction and double error detection is frequently used for error processing, that is, a one-bit error can be corrected, and a two-bit error can be detected. However, this error processing method has a problem that multiple bit errors are uncorrectable and undetectable, and if an error in directory data is unrecoverable, an error in cache coherence processing is caused, that is, an error occurs during memory access, which makes the data processing of the entire CC-NUMA system erroneous and causes a breakdown of the CC-NUMA system. In addition, a single-bit error may also change into a multi-bit error over time, which may also make the CC-NUMA system unavailable.